Latches flip-flops registers and timing discipline

A sequential circuit stores state. Its next behavior can depend on previous inputs as represented by that state.

An active-high D latch is transparent while enable is high; when enable is low, it holds its stored value. A positive-edge-triggered D flip-flop samples near a rising clock edge. A register groups storage elements to hold multiple bits. Reset behavior must specify polarity and whether reset is synchronous or asynchronous.

Setup time is how long D must be stable before the sampling edge. Hold time is how long it must remain stable afterward. Clock-to-Q is the delay between the active edge and a corresponding output change. Clock frequency limits depend on maximum data-path delay and setup; hold constraints depend on minimum delay. Slowing the clock does not automatically fix a hold violation.

For a master/slave circuit, determine which latch is enabled from its actual enable polarity and connections. Names like “Latch A” do not identify the transparent latch by themselves. Do not answer a diagram-specific question from a caption alone.

Check yourself: an active-high latch with enable 0 stores its previous output even if D changes.